The performance of small transistors, such as MOSFETs, can be affected by a short-channel effect commonly referred to as “punchthrough.” Punchthrough can be observed when a depletion region generated, for example, by the drain region of a MOSFET, contacts or comes into close proximity with an opposing depletion region generated by the opposing source region of the MOSFET. The contact of the depletion regions can cause charge to transfer between the source and drain region regardless of the voltage supplied to the gate. Therefore, MOSFETs affected by punchthrough may lose the ability to function as a switch (i.e., to turn off completely).
To reduce or prevent short-channel effects, it is known to form a recessed gate electrode having a small critical dimension and a long channel. Recessed gate electrodes are described herein with reference to FIGS. 1 through 3. FIG. 1 is a plan view of a typical MOS transistor. FIG. 2 is a cross-sectional view of the MOS transistor of FIG. 1, taken along the line I-I′. FIG. 3 is a cross-sectional view of the MOS transistor of FIG. 1, taken along the line II-II′.
As shown in FIGS. 1 through 3, isolation regions 12 are formed on an integrated circuit substrate 10 to define an active region A in the integrated circuit substrate 10, using techniques know to those having skill in the art. Next, a portion of the active region A, in which a gate electrode is subsequently formed, is etched to form a gate trench (or a recess) 15 to predetermined width and depth. The width of the gate trench 15 is less than or about equal to a width of the gate electrode, and the depth of the gate trench 15 is can be based on the channel length of the MOS transistor. Next, a surface of the integrated circuit substrate 10 including the gate trench 15 is oxidized to form a gate oxide layer 18. Thereafter, the gate trench 15 is filled with a conductive material and then patterned, thereby forming a gate electrode 20. The gate electrode 20 has a critical dimension W and a channel length CL which corresponds to a length of the outline of the gate trench 15 in the cross-sectional view shown in FIG. 2.
However, the MOS transistor of FIG. 1 may have some disadvantages. As shown in FIGS. 2 and 3, the gate trench 15, in which the gate electrode 20 is formed, can have a tapered side wall. The tapered side wall can be caused when the etch gas does not penetrating deeply enough into the integrated circuit substrate 10, i.e., the amount of etching provided by the gas may decrease as the depth of the recess is increased. The tapered side wall of the gate trench 15 can cause the channel length of the transistor to be non-uniform. For example, as shown in FIG. 3, the channel length corresponding to cross-section a of the transistor (hereinafter referred to as the “flat transistor” region), which is near or at the center of the active region A, can be different from the channel length corresponding to cross-section b (hereinafter referred to as the “corner transistor” region) which is located at an edge of the active region A.
FIG. 4 is a cross-sectional view comparing the respective channel lengths of the flat transistor region a and the corner transistor region b. A gate trench 15 is formed to a desired depth in a region of the trench 15 corresponding to the flat transistor region a of FIG. 3, thereby obtaining a channel length CL1. In contrast, the channel formed in a corner region of the trench 15 corresponding to the corner transistor region b of FIG. 3, is shallow compared to the channel of the flat transistor region a. Therefore, the length of the channel CL2 is less than the channel length CL1.
Since the corner transistor region b of FIG. 3 has a shorter channel length than the flat transistor region a of FIG. 3, a threshold voltage Vthb in the corner transistor region b can be less than a threshold voltage Vtha of the flat transistor region a. As a result, two different threshold voltages Vthb and Vtha can be observed in the active region as shown in FIG. 5. This phenomenon can cause a current Ioff to be generated unless a gate voltage is applied to the transistor.